This invention relates to a multiprocessor system which comprises a memory resource and a plurality of processors operated in cooperation with the memory resource.
A multiprocessor system of the type described is disclosed by Shinji Nanba in U.S. Pat. No. 4,665,484 assigned to the present assignee, NEC, and is effective to share a memory resource of a main memory by a plurality of processors which concurrently execute a plurality of programs and which are connected to the main memory through buses. In this connection, the memory resource may be called a shared resource which defines a common address space. From this fact, it is readily understood that the shared resource is logically coupled to all of the processors, although it is physically remote from the processors through the buses.
In the multiprocessor system, let a first one of the processors execute a first one of the programs and access the shared resource while the shared resource is being used by another one of the processors. In this case, execution of the first program is awaited in the first processor until reception of an unlock signal indicative of availability of the shared resource. Thus, all of the processors individually execute the programs by the use of a single common address space. This means that all the processors are coupled to one another via the single common address space.
With this structure, every one of the processors is level in operation with one another and therefore can become a control processor when a fault takes place in the multiprocessor system.
However, the microprocessor system requires an intricate bus arbiter to avoid competition or collision of requests which are issued from the processors to use the buses.
Moreover, it is to be noted that the common address space is not used except for a particular purpose because the common address space is physically remote from the processors through the buses. Therefore, the common address space is useless as long as a usual operation is carried out in each processor.